Playstation 3 Processor

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The Cell processor manufactured with a 90nm process will have 234 million transistors and a prototype die size of 221mm square.
By James Yu

Posted Monday, February 7th 2005


The next-generation Cell processor will consist of a single 64-bit Power processing core with eight synergistic processing units. Top engineers from IBM, Sony, and Toshiba made the disclosure at a press conference held at the opening of the International Solid-State Circuits Conference in San Francisco. The Cell triumvirate revealed last November that the processor would have a multicore architecture, but engineers did not reveal how many processing cores each Cell chip would have.


The Cell processor will power Sony's next-generation PlayStation 3 console.

The Cell processor will be at the core of Sony's soon-to-be-announced PlayStation 3 console system, and the chip will also find its way into several different applications that range from workstations to television sets.

The Cell processor will offer a tremendous amount of parallelism with its eight synergistic processing cores working in conjunction with the single Power control processor. SCEI vice president of microprocessor development Masakazu Suzuoki adds that the first Cell implementation only has eight synergistic cores, but the architecture is flexible enough to allow for additional cores. Current desktop processors, such as the Intel Pentium 4 and the AMD Athlon 64, only have a single processing core, but both companies plan to release dual-core desktop processors later this year.

The Cell processor manufactured with a 90nm process will have 234 million transistors and a prototype die size of 221mm square. The Intel Pentium 4 "Prescott" processor, by contrast, also uses the 90nm process, but it only has 125 million transistors and a 122mm square die size. Much of the Cell real estate is taken up by the multiple synergistic cores and a sizable amount of on-chip memory. The Cell has 512KB of L2 cache, and each synergistic processing unit has 256KB of cache memory.

The Cell uses Rambus XDR and FlexIO technology to move data in and out of the chip at speeds approaching 100 gigabytes per second. The XDR memory interface can push 30 gigabytes per second at 3.2GHz, and the FlexIO bus running at 6.4GHz has a maximum throughput of 72 gigabytes per second.

Even with the huge transistor count and large die size, the Cell development team has achieved clock speeds greater than 4GHz in internal testing. According to Jim Kahle, IBM Fellow and director of technology for the Design Center for Cell Technology, "We're not just going after the frequency race. We've pushed both frequency and parallelism at the same time." Even though the design group has demonstrated speeds greater than 4GHz, Kahle adds that it's ultimately up to the manufacturer to determine final clock speed, since the most-efficient clock speed, with regard to power consumption, won't be the maximum operating speed.

The Cell's multiple cores open up a variety of programming models in terms of thread assignment and resource management. The Power processor unit is capable of processing two threads, and each synergistic processor can handle a single thread each--for a total of 10 total concurrent threads--which introduces a new problem of determining how to best use all the processor resources.

According to Kahle, "We had a significant number of software engineers working on programming models for the Cell architecture. ... There are a number of different ways to approach the parallelism available in this chip, and we're going to make those available to people." The Cell team will develop the basic software models and then share the software design process with open-source communities to promote future development.

IBM will produce the processor using a 90nm manufacturing process in East Fishkill, New York, and Sony will manufacture the chip at its Nagasaki, Japan, fabrication plant using an advanced 65nm process.

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